(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and apparatus that provide uniform polishing when applying the process of Chemical Mechanical Polishing to the surface of a semiconductor wafer.
(2) Description of the Prior Art
The present invention relates to the technology of polishing or planarizing semiconductor surfaces including substrate surfaces during or after the process of processing these surfaces. The creation of semiconductor surfaces typically includes the creation of active devices in the surface of the substrates, the polishing of semiconductor surfaces can occur at any time within the sequence of processing semiconductors where such an operation of polishing is beneficial or deemed necessary.
That good surface planarity during the creation of semiconductor devices is of prime importance in achieving satisfactory product yield and in maintaining target product costs is readily evident in light of the fact that a semiconductor device typically contains a multiplicity of layers that form a structure of one or more layers superimposed over one or more layers. Any layer within that structure that does not have good planarity leads to problems of increased severity for the overlying layers. Most of the processing steps that are performed in creating a semiconductor device involve steps of photolithography that critically depend on being able to sharply define device features, a requirement that becomes increasingly more important where device features are in the sub-micron range or even smaller, down to about 0.1 um. Planarity directly affects the impact that light has on the surface of for instance a layer of photoresist, a layer which is typically used for patterning and etching the various layers that make up a semiconductor device. Lack of planarity leads to light diffusion which leads to poor depth of focus and a limitation on feature resolution (features such as adjacent lines cannot be closely spaced, a key requirement in today's manufacturing environment). This requirement, although of a general nature, can take on special stringency dependent on the material, for instance a relatively frequently used metal such as copper, that is being polished. Copper, typically applied using the damascene process for the creation of conductive lines and vias, is one of the most promising technologies to reduce RC delay as well as to implement the shrinkage of metal interconnect line structures. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. For this, Chemical Mechanical Polishing (CMP) of inlaid copper is required to form the copper wiring. One of the major problems that is encountered when polishing inlaid copper patterns is the damage that is caused on the copper trench as a consequence of the polishing process.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after CMP and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
During the Chemical Mechanical Planarization (CMP) process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to its increased use in the fabrication of complex integrated circuits.
It is well known in the art that, in the evolution of integrated circuit chips, the process of scaling down feature size results in making device performance more heavily dependent on the interconnections between devices. In addition, the area required to route the interconnect lines becomes large relative to the area occupied by the devices. This normally leads to integrated circuit chips with multilevel levels of interconnect lines. The chips are often mounted on multi-chip modules that contain buried wiring patterns to conduct electrical signals between the various chips. These modules usually contain multiple layers of interconnect metallization separated by alternating layers of an isolating dielectric. Any conductor material that is used in a multilevel interconnect has to satisfy certain essential requirements such as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) and ease of processing.
FIG. 1 shows a Prior Art CMP apparatus. A polishing pad 20 is attached to a circular polishing table 22 that rotates in a direction indicated by arrow 24 at a rate in the order of 1 to 100 RPM. A wafer carrier 26 is used to hold wafer 18 facedown against the polishing pad 20. The wafer 18 is held in place by applying a vacuum to the backside of the wafer (not shown). The wafer 18 can also be attached to the wafer carrier 26 by the application of a substrate attachment film (not shown) to the lower surface of the wafer carrier 26. Slurry 23 is supplied to the surface of the wafer 20 that is being polished. The wafer carrier 26 also rotates as indicated by arrow 32, usually in the same direction as the polishing table 22, at a rate on the order of 1 to 100 RPM. Due to the rotation of the polishing table 22, the wafer 18 traverses a circular polishing path over the polishing pad 20. A force 28 is also applied in the downward vertical direction against wafer 18 and presses the wafer 18 against the polishing pad 20 as it is being polished. The force 28 is typically in the order of 0 to 15 pounds per square inch and is applied by means of a shaft 30 that is attached to the back of wafer carrier 26.
A typical CMP process involves the use of a polishing pad made from a synthetic fabric and a polishing slurry, which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles.
Abrasive interaction between the wafer and the polishing pad is created by the motion of the wafer against the polishing pad. The pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals that comprise an insulating layer of the wafer. The size of the silicon dioxide particles controls the physical abrasion of surface of the wafer.
The polishing pad is typically fabricated from a polyurethane (such as non-fibrous polyurethane, cellular polyurethane or molded polyurethane) and/or a polyester-based material. Pads can for instance be specified as being made of a microporous blown polyurethane material having a planar surface and a Shore D hardness of greater than 35 (a hard pad). Semiconductor polishing pads are commercially available such as models IC1000 or Scuba IV of a woven polyurethane material.
The mechanical configuration of a typical CMP can contain a number of different arrangements. For instance, two different polishing belts can be used whereby the first belt is essentially used to perform one type of polish (for instance a copper polish that is aimed at eliminating copper corrosion) while the second belt is essentially aimed at performing a second type of polish (for instance a TaN polish where the TaN is used as the barrier layer of a damascene structure). In many of the CMP arrangements, a belt is used to transport the wafers with the exposed, to be polished surface of the wafer facing upwards. Above and aligned with this transportation belt is an arrangement of rotating polishing heads onto which polishing pads are mounted. The rotating polishing pads are brought into contact with the surface that is to be polished while the substrate continues to proceed in the direction into which it is being transported.
A number of parameters are known that determine and control the polishing operation, these parameters are:
downforce applied to the polishing pad, typically between 3 psi and 6 psi PA1 backside pressure applied to the rotating wafer, typically between 2 psi and 4 psi PA1 slurry flow, typically between 200 sccm and 400 sccm PA1 head speed, typically between 5 rpm and 20 rpm PA1 belt speed, typically between 75 fpm and 400 fpm, and PA1 DIW rinse time, typically between 0 seconds and 10 seconds and 30 seconds and 60 seconds. PA1 non-uniformity of surface thickness between the center of the wafer and the wafer perimeter, and PA1 variation in the Depth Of Focus (DOF) across the surface of the polished wafer.
It is clear that where a process of CMP is aimed at polishing a surface based on certain chemical components or materials that are present in its surface and that must be removed from the surface, the slurry composition and the resulting abrasive action of the slurry are key parameters when applying the process of CMP to the surface. Implied in the above listed parameters is that the relative speed differential between the surface of the wafer a that is being polished and the polishing pad is also one of the key parameters in determining the polishing action.
With the polishing arrangements that are presently used, the rotating polishing table contains one single polishing pad. It is clear that with one polishing pad the requirement of uniform polishing speed across the surface that is being polished is very difficult to accomplish, most notably in view of the obvious difference in relative speed between the polishing pad and the wafer surface when progressing from the center of the wafer to its perimeter. The ratio between the backpressure that is applied to the rotating wafer and the downforce that is applied to the polishing pad is the main parameter that controls the polishing action. The results of the polishing action are measured in parameters of thickness non-uniformity and surface planarity, both parameters as they relate to the surface that has been polished. The present method of using one polishing pad has the following disadvantages:
U.S. Pat. No. 5,941,758 (Mack) shows a multi-part annular polish pad that applies different pressures to different radiuses of the wafer. This invention differs from the present invention in that this invention teaches the application of different pressures to different portions of the backside of the substrate by means of a multiple pressure zone backpressure wafer carrier. Multiple air channels are provided to provide the multiple pressure zones across the backside of the substrate that is being polished. This invention does not address multiple polishing pads that are arranged in a concentric manner.
U.S. Pat. No. 5,899,745 (Kim et al.) shows a CMP with an underpad with different compression regions.
U.S. Pat. No. 5,624,304 (Pasch et al.), U.S. Pat. No. 5,605,499 (Sugiyama et al.) and U.S. Pat No. 5,403,228 (Pasch) show CMP systems for uniform CMP across wafers. U.S. Pat. No. 5,624,304 (Pasch et al.) and U.S. Pat. No. 5,605,499 (Sugiyama et al.) provide a method of mounting different polishing pads to one platen and do not provide a method of separate platen bodies. U.S. Pat. No. 5,403,228 (Pasch) shows a method of mounting a two-layer polishing pad, these polishing pads may be of different polishing hardness and thereby provide selectivity of the polishing speed across the surface of the substrate that is being polished.